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| 33C408 4 Megabit (512K x 8-Bit) CMOS SRAM Memory Logic Diagram FEATURES: * RAD-PAK(R) Technology radiation-hardened against natural space radiation * 524,288 x 8 bit organization * Total dose hardness: - > 100 krad (Si), depending upon space mission * Excellent Single Event Effect * - SELTH: > 68 MeV/mg/cm2 * - SEUTH: = 3 MeV/mg/cm2 - SEU saturated cross section: 6E-9 cm2/bit * Package: - 32-Pin RAD-PAK(R) flat pack - 32-Pin Non-RAD-PAK(R) flat pack * Fast access time: - 20, 25, 30 ns maximum times available * Single 5V + 10% power supply * Fully static operation - No clock or refresh required * Three state outputs * TTL compatible inputs and outputs * Low power: - Standby: 60 mA (TTL); 10 mA (CMOS) - Operation: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30 ns) DESCRIPTION: Maxwell Technologies' 33C408 high-density 4 Megabit SRAM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. Using Maxwell's radiation-hardened RAD-PAK(R) packaging technology, the 33C408 realizes a high density, high performance, and low power consumption. Its fully static design eliminates the need for external clocks, while the CMOS circuitry reduces power consumption and provides higher reliability. The 33C408 is equipped with eight common input/output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. The 33C408 features the same advanced 512K x 8-bit SRAM, high-speed, and low-power demand as the commercial counterpart. Maxwell Technologies' patented RAD-PAK packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 04.16.02 REV 8 All data sheets are subject to change without notice 1 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM 33C408 TABLE 1. PINOUT DESCRIPTION PIN 12-5, 27, 26, 23, 25, 4, 28, 3, 31, 2, 30, 1 29 22 24 13-15, 17-21 32 16 SYMBOL A0-A18 WE CS OE I/O 1-I/O 8 VCC VSS DESCRIPTION Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power (+5.0V) Ground TABLE 2. 33C408 ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on VCC supply relative to VSS Voltage on any pin relative to VSS Power Dissipation Storage Temperature Operating Temperature SYMBOL VCC VIN, VOUT PD TS TA MIN -0.5 -0.5 --65 -55 MAX 7.0 VCC +0.5 1.0 +150 +125 UNIT V V W C C TABLE 3. DELTA LIMITS PARAMETER ICC1 ISB ISB1 ILI VARIATION 10% of stated vaule in Table 6 10% of stated vaule in Table 6 10% of stated vaule in Table 6 10% of stated vaule in Table 6 04.16.02 REV 8 All data sheets are subject to change without notice 2 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 4. 33C408 RECOMMENDED OPERATING CONDITIONS (VCC = 5.0 + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE NOTED) PARAMETER Supply Voltage Ground Input High Voltage 1 Input Low Voltage 2 Thermal Impedance 1. VIH (max) = VCC +2.0V ac (pulse width < 10 ns) for I < 20 mA 2. VIL (min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA SYMBOL VCC VSS VIH VIL MIN 4.5 0 2.2 -0.5 -MAX 5.5 0 33C408 UNIT V V V V C/W VCC+0.5 0.8 1.21 JC TABLE 5. 33C408 DC ELECTRICAL CHARACTERISTICS (VCC = 5V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Current -20 -25 -30 Standby Power Supply Current CMOS Standby Power Supply Current Input Capacitance 1 Output Capacitance 1 1. Guaranteed by design. SYMBOL ILI ILO VOL VOH ICC CONDITION VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL, VOUT =VSS to VCC IOL = 8mA IOH = -4mA Min cycle, 100% Duty, CS=VIL, IOUT=0mA, VIN = VIH or VIL SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 ---1, 2, 3 1, 2, 3 --180 170 160 60 10 mA mA MIN -2 -2 -2.4 MAX 2 2 0.4 -UNIT A A V V mA ISB ISB1 CS = VIH, Min Cycle CS > VCC - 0.2V, f = 0 MHz, VIN > VCC - 0.2V or VIN < 0.2V VIN = 0V, f = 1MHz, TA = 25 C VI/O = 0V CIN CI/O 1, 2, 3 4, 5, 6 --- 7 8 pF pF TABLE 6. 33C408 AC TEST CONDITIONS AND CHARACTERISTICS (VCC = 5.0 + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE NOTED) PARAMETER Input Pulse Level Output Timing Measurement Reference Level 04.16.02 REV 8 MIN 0.0 -- TYP --- MAX 3.0 1.5 UNITS V V All data sheets are subject to change without notice 3 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 6. 33C408 AC TEST CONDITIONS AND CHARACTERISTICS (VCC = 5.0 + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE NOTED) PARAMETER Input Rise/Fall Time Input Timing Measurement Reference Level MIN --TYP --MAX 3.0 1.5 33C408 UNITS ns V TABLE 7. 33C408 AC CHARACTERISTICS FOR READ CYCLE (VCC = 5V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Read Cycle Time -20 -25 -30 Address Access Time -20 -25 -30 Chip Select Access Time -20 -25 -30 Output Enable to Output Valid -20 -25 -30 Chip Enable to Output in Low-Z -20 -25 -30 Output Enable to Output in Low-Z -20 -25 -30 Chip Deselect to Output in High-Z -20 -25 -30 Output Disable to Output in High-Z -20 -25 -30 Output Hold from Address Change -20 -25 -30 SYMBOL tRC SUBGROUPS 9, 10, 11 20 25 30 tAA 9, 10, 11 ---tCO 9, 10, 11 ---tOE 9, 10, 11 ---tLZ 9, 10, 11 ---tOLZ 9, 10, 11 ---tHZ 9, 10, 11 ---tOHZ 9, 10, 11 ---tOH 9, 10, 11 3 5 6 04.16.02 REV 8 MIN TYP ------------3 3 3 0 0 0 5 6 8 5 6 8 ---- MAX ---- UNIT ns ns 20 25 30 ns 20 25 30 10 12 14 ---ns ---ns ---ns ---ns ---ns ns All data sheets are subject to change without notice 4 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 7. 33C408 AC CHARACTERISTICS FOR READ CYCLE (VCC = 5V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Chip Select to Power Up Time -20 -25 -30 Chip Select to Power Down Time -20 -25 -30 SYMBOL tPU SUBGROUPS 9, 10, 11 ---tPD 9, 10, 11 ---10 15 20 0 0 0 MIN TYP 33C408 MAX ---ns ---UNIT ns TABLE 8. 33C408 FUNCTIONAL DESCRIPTION CS H L L L 1. X = don't care. WE X1 H H L OE X1 H L X1 MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT ISB, ISB1 ICC ICC ICC Subgroups TABLE 9. 33C408 AC CHARACTERISTICS FOR WRITE CYCLE (VCC = 5V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Write Cycle Time -20 -25 -30 Chip Select to End of Write -20 -25 -30 Address Setup Time -20 -25 -30 Address Valid to End of Write -20 -25 -30 SUBGROUPS 9, 10, 11 SYMBOL tWC 20 25 30 9, 10, 11 tCW 14 15 17 9, 10, 11 tAS 0 0 0 9, 10, 11 tAW 14 15 17 ------------ns ------ns ------ns MIN TYP MAX UNIT ns 04.16.02 REV 8 All data sheets are subject to change without notice 5 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM TABLE 9. 33C408 AC CHARACTERISTICS FOR WRITE CYCLE (VCC = 5V + 10%, TA = -55 TO +125 C, UNLESS OTHERWISE SPECIFIED) PARAMETER Write Pulse Width (OE High) -20 -25 -30 Write Recovery Time -20 -25 -30 Write to Output in High-Z -20 -25 -30 Write Pulse Width (OE Low) -20 -25 -30 Data to Write Time Overlap -20 -25 -30 End Write to Output Low-Z -20 -25 -30 Data Hold from Write Time -20 -25 -30 SUBGROUPS 9, 10, 11 SYMBOL tWP 14 15 17 9, 10, 11 tWR 0 0 0 9, 10, 11 tWHZ ---9, 10, 11 tWP1 ---9, 10, 11 tDW 9 10 11 9, 10, 11 tOW ---9, 10, 11 tDH 0 0 0 ---6 7 8 ---20 25 30 5 5 6 ------MIN TYP 33C408 MAX ---ns ---ns ---ns ---ns ---ns ---ns ---UNIT ns 04.16.02 REV 8 All data sheets are subject to change without notice 6 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM 33C408 FIGURE 1. AC TEST LOADTIMING WAVEFORM OF READ CYCLE(1) FIGURE 2. TIMING WAVEFORM OF READ CYCLE (2) Read Cycle Notes: 1. WE is high for read cycle. 2. All read cycle timing is referenced form the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and from device to device. 5. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS = VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention condition is necessary during read and write cycle. 04.16.02 REV 8 All data sheets are subject to change without notice 7 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM FIGURE 3. TIMING WAVEFORM OF WRITE CYCLE(1) 33C408 FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE(2) FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (3) 04.16.02 REV 8 All data sheets are subject to change without notice 8 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM 33C408 WRITE CYCLE NOTE: All write cycle timing is referenced from the last valid address to the first transition address. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low: A write ends at the earliest transition among CS going high and WE going high. t is measured from beginning of write to the end of write. t is measured from the later of CS going low to end of write. 3. 4. t is measured from the address valid to the beginning of write. 5. t is measured form the end of write to the address change. TWR applied in case a write ends as CS, or WR going high. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. 6. Inputs of opposite phase of the output must not be applied because bus contention can occur. For common I/O applications, minimization or elimination of bus contention conditions is necessary 7. during read and write cycle. 8. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. D is the read data of the new address. 9. 10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. WP CW AS WR OUT 1. 2. 04.16.02 REV 8 All data sheets are subject to change without notice 9 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM 33C408 32 PIN RAD-PAK(R) FLAT PACKAGE SYMBOL MIN A b c D E E1 E2 E3 e L Q S1 N F32-06 Note: All dimensions in inchesImportant Notice: 0.390 0.026 0.005 0.120 0.013 0.008 -0.635 -0.550 0.030 DIMENSION NOM 0.135 0.015 0.010 0.930 0.645 -0.565 0.040 0.050 BSC 0.400 0.098 0.082 32 0.410 --MAX 0.155 0.020 0.012 0.940 0.655 0.690 --- 04.16.02 REV 8 All data sheets are subject to change without notice 10 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM 33C408 These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies' products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies' liability shall be limited to replacement of defective parts. 04.16.02 REV 8 All data sheets are subject to change without notice 11 (c)2002 Maxwell Technologies All rights reserved. 4 Megabit (512K x 8-Bit) CMOS SRAM Product Ordering Options 33C408 Model Number 33C408 XX F X -XX Feature Access Time Option Details 20 = 20 ns 25 = 25 ns 30 = 30 ns Screening Flow Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25C) I = Industrial (testing @ -55C, +25C, +125C) Package F = Flat Pack Radiation Feature RP = RAD-PAK(R) package RT = Non-RAD-PAK(R) package Base Product Nomenclature 4 Megabit CMOS SRAM 04.16.02 REV 8 All data sheets are subject to change without notice 12 (c)2002 Maxwell Technologies All rights reserved. |
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